PIB TrackerRs 1,27,500 crore of public outlay against Rs 1.64 lakh crore of private
SEMICON India 2026 closed with 12 projects approved, three in commercial production, and 12 nm as the most advanced process node anyone put on display.
What happened
- SEMICON India 2026, the fifth edition, ran 17-19 September 2026 at Yashobhoomi, New Delhi, with 600+ exhibitors.
- Theme: "Silicon to Systems: Building the Ecosystem" - the shift from chip design to the full value chain.
- C-DAC showed the AUM HPC-AI Processor, the RUDRA-AUM compute node and an indigenous 64-bit RISC-V processor.
- Aheesa showed a 1 Gbps optical line terminal serving about 64 homes, on the Indian Vihan stack and a C-DAC RISC-V chip.
- The DLI Scheme and C2S Programme were named as the instruments behind the design-side numbers.
For Prelims
- Semicon 2.0: approved by the Union Cabinet in July 2026, outlay Rs 1,27,500 crore. Six pillars: design; machines and materials; more fabs; advanced packaging; R&D; talent development.
- Semicon India Programme record: 12 projects, six states, commitments over Rs 1.64 lakh crore, three in commercial production.
- RISC-V: an open instruction set architecture - royalty-free, which is why it is the base for indigenous processor efforts. C-DAC's is 64-bit.
- DLI: the Design Linked Incentive scheme. C2S: Chips to Startup. Both are served by the ChipIN Centre, which provides design tools and foundry access.
- Tape-out: the point at which a finished chip design is sent to a foundry for fabrication - the milestone Netrasemi reached at 12 nm.
- Advanced packaging (ATMP/OSAT): assembly, testing, marking and packaging - a separate pillar from fabrication, and where most approved Indian projects sit.
- C-DAC: the Centre for Development of Advanced Computing, under MeitY - the institutional home of the indigenous HPC and processor effort.
- The node ladder: smaller nm means denser, faster, more efficient logic. India's displayed work runs 180 nm to 12 nm; the leading global edge is several generations below that.
For UPSC: Semiconductors are now a standing Prelims and Mains topic, and this backgrounder carries the outlay, the project count, the conversion rate and the process nodes in one document. Use it on indigenisation and critical technology, on industrial policy where the public share of the investment is unusually large, and on supply-chain resilience, where the design-versus-fabrication distinction is the thing most answers get wrong.
What it is NOT: The release gives no wafer capacity for any approved project, no target node for any fab, and no timeline for the nine projects not yet in commercial production. It does not say what the three producing facilities actually make, or at what node. It gives no disbursement figure against the Rs 1,27,500 crore outlay, so how much of Semicon 2.0 has been spent is unknown. It gives no import-substitution or self-sufficiency figure, which is the whole justification for the spending. The 300 chip designs come with no count of how many reached silicon or commercial sale. And nothing is said about equipment, ultra-pure materials or EDA tools, all of which remain imported.
For Mains
Syllabus: GS3.12 · GS3.13 · Linkage L2
Anchor
Semicon 2.0 carries a public outlay of Rs 1,27,500 crore against private investment commitments of Rs 1.64 lakh crore across 12 approved projects. The state is putting up roughly seventy-eight paise for every rupee industry has committed - an unusually high public share for a manufacturing programme.
Substantiation (data)
The design ecosystem is further along than the fabrication one, and the numbers show it. More than one lakh engineers across 500 organisations have produced over 300 chip designs and four crore hours of tool usage through the ChipIN Centre. Three of twelve approved facilities are in commercial production - a twenty-five per cent conversion since the programme began.
Position
Design-first is the correct sequence for India, and the exhibits argue it well. RISC-V is royalty-free, so an indigenous 64-bit processor is achievable without licensing a foreign ISA, and Aheesa's optical line terminal - Indian software stack on an Indian RISC-V chip, serving 64 homes at 1 Gbps - shows what a complete domestic stack looks like at product level rather than at slide level.
Counterpoint
The process nodes on display set the honest limit. The most advanced Indian tape-out named is 12 nm, and the silicon-proven range is 180 nm to 16 nm. That is a legitimate and commercially useful band - it covers automotive, industrial, power and most edge AI - but it is not the frontier, and nothing in the release claims a path to it.
Problematisation
What is absent is capacity. No wafer volume, no target node and no timeline appear for any of the nine projects not yet producing, and the three that are producing are not described. Nor is there any disbursement figure against the outlay, or any measure of import substitution - which is the entire policy justification.
Conclusion
Read the conversion rate rather than the outlay. India has built a real chip-design base with measurable output, and the fabrication question turns on whether the remaining nine projects reach production - not on how large the sanctioned figure is.
Deploys into: Semiconductor policy and indigenisation · Industrial policy and public investment share · Critical technology supply chains · Design versus fabrication capability
Ministry of Electronics & IT · 2026-09-22 · PRID 2313324 · PIB source ↗