PIB Tracker254 chips taped out by students, 175 of them at Mohali
The Chips to Start-ups programme has trained over 68,000 students towards a target of 85,000, given 332 institutions access to commercial chip design tools, and seen 254 designs actually fabricated.
What happened
- Chips to Start-ups aims to generate 85,000 industry-ready chip design personnel.
- More than 68,000 students have been trained so far.
- 332 academic institutions have access to advanced EDA tools.
- Institutions have taped out 254 chip designs.
- 175 were at the 180 nm node at SCL Mohali and 79 at overseas foundries.
For Prelims
- C2S: the Chips to Start-ups programme under MeitY, targeting 85,000 trained personnel at B.Tech, M.Tech and PhD levels.
- EDA: Electronic Design Automation — the commercial software chips are designed on (Synopsys, Cadence, Siemens EDA and others).
- Tape-out: the point at which a finished design is committed to fabrication — the step that separates a design exercise from a chip.
- SCL Mohali: the Semi-Conductor Laboratory, India's government fab, operating at the 180 nm node.
- The split: 175 designs at SCL Mohali, 79 at overseas foundries, of 254 total.
- Node size: 180 nm is a mature node — adequate for teaching, analog and power devices, far behind leading-edge logic.
- India Semiconductor Mission: the wider programme covering fabs, ATMP/OSAT and design linked-incentive schemes.
- DLI scheme: the Design Linked Incentive supporting domestic fabless chip design companies.
For UPSC: The design-side semiconductor card. Use it for the talent and toolchain constraint in chip design, SCL Mohali and mature nodes, the India Semiconductor Mission's design pillar, and why design capability is separable from fabrication capacity.
What it is NOT: Design capability is not fabrication capacity — 254 tape-outs at 180 nm and overseas foundries show students can design chips, not that India can manufacture advanced ones.
For Mains
Syllabus: GS3.13 · GS2.13 · Linkage L2
Anchor
A semiconductor policy that only builds fabs would be a factory without designers; this is the other half.
Substantiation (data)
68,000-plus trained against a target of 85,000, EDA tool access at 332 institutions, and 254 designs taped out — 175 at SCL Mohali and 79 abroad.
Exemplification
Andhra Pradesh's 23 institutions alone logged over 4.34 lakh tool-hours on commercial design software.
Problematisation
Tape-outs at 180 nm and at foreign foundries expose the gap the programme cannot close on its own: India has no leading-edge fabrication to absorb these designers domestically.
Way-forward
Link C2S graduates to the Design Linked Incentive pipeline and to the fabs under construction, so trained designers have somewhere to go.
Position
Chip sovereignty begins with people who know how to design one — the fab is the second problem, not the first.
Deploys into: Frontier technology + education (GS3.13, GS2.13) · the talent and toolchain constraint in chip design, SCL Mohali and mature nodes, and the India Semiconductor Mission's design pillar.
Ministry of Electronics & IT · 2026-08-14 · PRID 2299338 · PIB source ↗