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Odisha, Intel and 3DGS sign glass-core substrate deal

A framework MoU to set up an advanced semiconductor packaging substrate plant near Bhubaneswar — India's first serious move into glass-core substrates.

What happened

Background & context

To read this MoU correctly, an aspirant must know where in the chip supply chain a "substrate" sits. Making a semiconductor has two broad stages. The front-end — wafer fabrication ("fab") — is where transistors are etched onto a silicon wafer using lithography; this is the glamorous, capital-heavy part dominated by TSMC, Samsung and Intel. The back-endassembly, testing, marking and packaging (ATMP/OSAT) — is where the finished die is cut, mounted, wired and sealed into the black package a phone or laptop actually uses. A substrate is the engineered base layer inside that package that carries the electrical connections between the silicon die and the circuit board. As chips get denser, the substrate has become a bottleneck of its own, and advanced packaging has turned into a frontier technology rather than a commodity step.

A glass-core substrate replaces the traditional organic (resin/laminate) core with a glass core. Glass offers better flatness, dimensional stability and the ability to support far finer, denser interconnects — qualities that matter for AI accelerators and high-performance processors that stitch many chiplets together. This is therefore not an ordinary assembly line; it is an entry point into a packaging technology that only a handful of global players are scaling. High-density interconnect (HDI) substrates, the other focus of the plant, pack more wiring into less area for compact, high-performance devices.

The deal sits under the India Semiconductor Mission (ISM), the Government of India's umbrella programme to build a domestic semiconductor and display manufacturing ecosystem. ISM was approved in 2021 with a financial outlay of about ₹76,000 crore and operates as an independent business division within the Digital India Corporation under the Ministry of Electronics & Information Technology (MeitY). ISM is the nodal agency that administers the incentive schemes for the sector: support for silicon semiconductor fabs, display fabs, compound semiconductors / sensors / discrete semiconductors, and crucially the Semiconductor ATMP/OSAT scheme that covers exactly the back-end packaging layer this Odisha plant belongs to. The same umbrella also houses the Design Linked Incentive (DLI) scheme for fabless chip design. The substrate plant is best read as a deliberate attempt to seed the packaging and materials end of the chain rather than chasing only a marquee wafer fab.

Odisha's involvement also matters. The State has positioned itself in electronics and chemicals, and an MoU of this scale signals that semiconductor activity in India is spreading beyond the first cluster of projects in Gujarat and Assam. The Bhubaneswar–Khurda corridor gives the project an industrial base, while the phased five-to-six-year horizon is consistent with how packaging and substrate capacity is built — capacity is added in stages as yields and demand mature.

How it compares to a peer step. It is useful to set the substrate plant against the projects already approved under ISM. India's first sanctioned units are dominated either by a full silicon fab (the Tata Electronics–PSMC project at Dholera in Gujarat, which etches wafers) or by conventional ATMP/OSAT assembly-and-test lines (such as the Micron unit at Sanand and the Tata and CG Power packaging projects). Glass-core and HDI substrates sit one notch more specialised than ordinary OSAT: they are a materials-and-interconnect technology that feeds those packaging lines, closer to the cutting edge of how chiplets are joined. So while a fab makes the die and an OSAT unit packages it, a substrate plant supplies a critical input that both increasingly depend on — which is why the Ministry framed it alongside the materials and equipment entrants (Merck, Applied Materials, Lam Research, Tokyo Electron) rather than alongside the fabs.

On the partners. Intel is one of the few global firms publicly developing glass-core substrate technology for high-performance and AI processors, which is why its role here is described as supplying technology know-how and process expertise rather than acting as the State investor. 3DGS Inc. is the US-based specialist partner to the agreement; the Government of Odisha is the host-State counterparty providing the location and State-level facilitation. The three-way structure — host State, technology major, specialist firm — is a template India has used to bring frontier manufacturing onshore without first owning the underlying process itself.

For Prelims

What it is NOT: This is not a wafer fabrication (fab) plant — no transistors are etched here; it is a back-end packaging/substrate facility. The substrate is not the silicon chip itself; it is the base layer that carries connections in the package. It is also not an ISM-funded project being announced — it is a framework MoU (a statement of intent) that builds on ISM, not a sanctioned incentive grant. And Intel here is the technology partner, not necessarily the equity owner of the facility.

The full set worth holding (India's semiconductor map): ISM's four incentive tracks are (1) silicon fabs, (2) display fabs, (3) compound semiconductors / sensors / ATMP-OSAT packaging, and (4) the separate DLI design scheme. India's first cluster of approved projects sits largely in Gujarat (Dholera, Sanand) and Assam (Morigaon); this Odisha MoU extends the footprint to a new State and into the specialised substrate/packaging niche. Knowing the fab-vs-ATMP-vs-design split, and that substrates and packaging are back-end, is what survives a "consider the following statements" question on this theme.

For UPSC: Odisha–Intel–3DGS MoU = an advanced packaging glass-core / HDI substrate plant in Bhubaneswar–Khurda, built on the India Semiconductor Mission; Intel = technology partner; substrates are the back-end packaging layer, not wafer fabrication.

Why it matters

India's semiconductor push has so far concentrated on fabs and conventional ATMP. The structural gap is in advanced packaging and substrates — a layer where supply is concentrated in a few countries and where demand is rising fastest because of AI and high-performance computing. A glass-core substrate facility addresses that gap directly: it moves India up the value chain into a technology-intensive, higher-margin segment rather than only labour-intensive assembly. It also diversifies the geography of India's chip ecosystem and deepens the US–India technology partnership, since Intel and 3DGS bring process expertise that India does not yet hold at scale. The honest caveat — which the release itself implies by calling this a framework MoU phased over years — is that intent is not yet capacity; realisation depends on financing, talent and yields.

For Mains

Exemplification
A concrete example of India climbing the semiconductor value chain — from assembly toward advanced packaging and glass-core substrates — when answering questions on indigenisation of strategic technology and reducing import dependence.
Substantiation
Supplies data points — a three-way MoU (Odisha–Intel–3DGS), phased over 5–6 years, in the Bhubaneswar–Khurda region, under the ISM (2021, ≈₹76,000 crore) — to back arguments on the spread and depth of India's chip ecosystem.
Problematisation
Illustrates the gap the policy admits: India's strength is in design and assembly, while substrates, packaging materials and equipment remain import-dependent — a vulnerability in any answer on technology sovereignty and supply-chain resilience.
Way-forward
Points to a route forward — partnering with global technology holders to localise the back-end and materials layer, and spreading capacity to new States like Odisha rather than a single cluster.
Deploys into: indigenisation and new technology (GS3.12); IT, electronics and IPR / building India's semiconductor ecosystem (GS3.13); India–US technology cooperation and supply-chain resilience.
Ministry of Electronics & IT · 2026-05-29 · PRID 2266614 · PIB source ↗