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India's first 3D glass chip-packaging unit breaks ground

Foundation stone laid at Info Valley, Bhubaneswar, for the country's first advanced 3D glass-substrate semiconductor packaging facility, cleared under the India Semiconductor Mission.

What happened

Background & context

Making a microchip runs through two broad halves. The front-end — fabrication, or the "fab" — etches transistors onto a silicon wafer in a process flow that can run hundreds of steps under extreme cleanliness. The back-end takes those finished wafers and turns them into usable devices: the wafer is diced, each die is assembled onto a substrate, the package is tested, marked and sealed. This back-end half is the work captured by the acronym ATMP — Assembly, Testing, Marking and Packaging (closely related to the term OSAT, Outsourced Semiconductor Assembly and Test). The Bhubaneswar facility is an ATMP/packaging unit, which is precisely why officials describe it as India's first advanced 3D packaging plant rather than a fab.

What makes this unit distinct is the substrate material. Conventional advanced packages route signals through an interposer or substrate made of silicon or organic laminate. This plant is built around an embedded glass substrate — glass panels into which interconnects and passive components are embedded. Glass offers a flat, dimensionally stable, low-loss platform that suits high-frequency and high-density routing, which is why such substrates are pitched for AI accelerators, high-performance computing and millimetre-wave 5G/6G parts. The output is described in 3DHI terms — 3D Heterogeneous Integration — where multiple dies (often from different process nodes, logic stacked with memory or analogue) are integrated vertically into one package rather than spread across a board.

The clearance sits under the India Semiconductor Mission (ISM), the nodal programme for building a domestic chip ecosystem. ISM operates as an independent business division within the Digital India Corporation under the Ministry of Electronics & Information Technology (MeitY), and administers the incentive umbrella commonly grouped as the Semicon India Programme, with a corpus that was announced at ₹76,000 crore. Its component schemes cover the whole chain: support for semiconductor fabs, display fabs, compound-semiconductor / silicon-photonics / sensor fabs and discrete units, the ATMP/OSAT scheme under which a packaging unit like this one qualifies, and the Design Linked Incentive (DLI) scheme for chip design. The mission is the policy vehicle behind the better-known approved projects — among them the Tata–PSMC fab in Dholera (Gujarat), the Tata (TSAT) and CG Power–Renesas and Micron and Kaynes packaging/assembly units in Gujarat — and now this glass-substrate unit in Odisha.

Odisha's position in this map is unusual. The release notes that it is the only State where both India's first compound-semiconductor fabrication unit and its first 3D glass-substrate packaging facility are being set up. Two semiconductor projects have already been approved for the State under ISM, with three more reported in the pipeline and discussions said to be underway with Intel. The State frames its own role through its IT, AI, GCC and Semiconductor Policies of 2025, which layer State-level capital support on top of the Central incentive — the ₹399.5 crore State component here is an example of that co-funding model.

It helps to place this unit within the wider set of semiconductor projects that India has approved, because UPSC questions on this theme often test whether an aspirant can sort fabs from packaging units and locate them by State. The fabrication (front-end) side includes the Tata Electronics–PSMC fab and the compound-semiconductor work concentrated largely in Gujarat. The packaging and assembly (back-end / ATMP) side includes Micron's assembly-and-test unit, the Tata (TSAT) packaging unit and the CG Power–Renesas–Stars unit, with Kaynes also in the assembly space — several of these clustered in Gujarat. Against that backdrop, the Odisha glass-substrate unit is notable on two counts: it is the first to use embedded glass substrates rather than silicon or organic ones, and it carries Odisha into a map that had been dominated by Gujarat. The point worth holding for revision is that packaging is the larger share of approved projects so far — India's near-term entry into chips is being led by the back-end as much as by marquee fabs.

The materials story behind the "glass" label is also worth a line. Advanced packaging has historically leaned on silicon interposers (precise but costly) and organic laminate substrates (cheaper but limited at high frequencies). Glass-core substrates sit between these: they are dimensionally stable, can be made in large rectangular panel formats rather than round wafers, and handle high-frequency signals with low loss — which is why they are being pursued for the densest AI and millimetre-wave packages. The "panel" capacity figure in the release (70,000 glass panels a year) reflects this panel-format processing, a different manufacturing geometry from the wafer-based flows of a fab.

For Prelims

What it is NOT: This is not a fabrication unit (a "fab"). A fab does the front-end — etching transistors onto wafers; this unit does the back-end — assembling, packaging and testing already-fabricated dies on glass substrates. It is also not the same as the compound-semiconductor fab separately being set up in Odisha. And "3D" here refers to 3D heterogeneous integration of stacked dies, not to 3D printing.
For UPSC: ATMP = Assembly, Testing, Marking and Packaging — the back-end of chip-making (distinct from front-end fabrication). This is India's first 3D glass-substrate packaging unit, runs under the India Semiconductor Mission (ISM, under MeitY), and sits in Odisha — the only State with both a compound-semiconductor fab and a glass-substrate packaging facility.

Why it matters

India's semiconductor push has, so far, been weighted toward the high-visibility fabs. But a chip is not finished until it is packaged and tested, and global packaging capacity is geographically concentrated — a structural choke-point that a fab alone does not solve. Building advanced packaging capacity at home addresses that gap: it lets dies fabricated elsewhere (or in India's own future fabs) be assembled, integrated and tested domestically, deepening the value chain and reducing dependence on a small number of overseas packaging hubs.

The choice of glass-substrate and 3D heterogeneous integration is what places the unit at the leading edge rather than the commodity end of packaging. These are the package types being designed for AI accelerators, high-performance computing and millimetre-wave communications — the workloads where conventional substrates run into signal-loss and density limits. Locating that capability in India, with a named end-use list that explicitly includes defence electronics, automotive radar and aerospace, gives the country a foothold in packaging for strategically sensitive systems, not only consumer electronics.

The release also frames the broader trajectory: electronics-manufacturing production is stated to have grown roughly six-fold over twelve years, with India described as the world's second-largest mobile-phone manufacturer and a leading exporter of mobile phones in 2025. The semiconductor build-out is the next layer of that story — moving from assembling finished electronics toward making and packaging the chips inside them. For Odisha specifically, anchoring two firsts (a compound-semiconductor fab and a glass-substrate packaging unit) seeds a regional cluster, with the supplier base, skilled workforce and ancillary investment that tends to follow an anchor plant.

For Mains

Substantiation
Concrete data point on the deepening of India's semiconductor value chain — ₹1,943.53 cr advanced-packaging unit (₹799 cr Central + ~₹399.5 cr State support) under the India Semiconductor Mission, capacity 70,000 glass panels and ~13,000 3DHI modules a year, serving AI, HPC, 5G/6G and defence electronics.
Exemplification
A textbook example of indigenisation of new and emerging technology (GS3.12): moving beyond device assembly into advanced chip packaging, and of how Central incentive schemes co-funded by State industrial policy (Odisha's 2025 semiconductor policy) attract anchor investment to a new region.
Position
Reflects the Government's stated strategy of building the full semiconductor chain — design, fabrication and ATMP/OSAT packaging — rather than fabs alone, with the back-end treated as a deliberate priority through the ATMP incentive scheme.
Problematisation
Highlights the gap such investment is meant to close — India's near-total dependence on a small set of overseas hubs for advanced packaging and testing, a back-end choke-point that a front-end fab does not by itself resolve.
Deploys into: indigenisation of technology and developing new technology (GS3.12); achievements of Indians in science & technology and IT/space/electronics (GS3.13); the semiconductor supply-chain debate; balanced regional industrial development and Centre–State co-investment in high-tech manufacturing.

Related: India Semiconductor Mission (ISM) · Science & Tech · This week's cards

Ministry of Electronics & IT · 2026-04-19 · PRID 2253549 · PIB source ↗