🔬 Science & TechMAINS · GS3.13

Semicon 2.0 to widen chip-design training reach

The India Semiconductor Mission's Chips-to-Startups talent pipeline is set to grow from 315 to 500 institutions under Semicon 2.0.

What happened

The Electronics & IT Ministry reported that under the Chips to Startups (C2S) initiative of the India Semiconductor Mission (ISM), the country has covered substantial ground in the past four years toward its ten-year goal of training 85,000 engineers in semiconductor design.
Industry-grade Electronic Design Automation (EDA) tools — backed by Synopsys, Cadence, Siemens, Renesas, Ansys and AMD — have been placed in 315 academic institutions across India.
Designs created by students are fabricated and tested at the Semiconductor Laboratory (SCL), Mohali, giving end-to-end exposure across Design, Fabrication, Packaging and Testing.
The programme has grown into what the Ministry calls the world's largest open-access EDA programme, having logged over 1.85 crore hours of tool usage.
Under India Semiconductor Mission 2.0 (Semicon 2.0), the EDA reach is to widen from 315 to 500 academic institutions, with participation spanning students "from Assam to Gujarat and Kashmir to Kanyakumari".
The Ministry framed the push against a global semiconductor market growing from roughly USD 800–900 billion to about USD 2 trillion, which is expected to need close to 2 million skilled professionals.

Background & context

The announcement sits inside India's wider bet on semiconductors, anchored by the India Semiconductor Mission (ISM). ISM was approved in 2021 as part of the larger Semicon India Programme and operates as an independent business division housed under the Digital India Corporation, a Section 8 (not-for-profit) company of the Ministry of Electronics & Information Technology (MeitY). Its mandate is to drive a long-term strategy for building a sustainable semiconductor and display manufacturing ecosystem — covering fabrication units, display fabs, compound-semiconductor and sensor units, and assembly-testing-marking-packaging (ATMP/OSAT) facilities — while also developing the human capital and design strength that such an ecosystem cannot function without.

Chip-making is usually divided into three broad layers: design (creating the circuit on a computer), fabrication (etching that design onto silicon wafers in a fab), and ATMP/OSAT (assembly, testing, marking and packaging of the finished die). India already has globally significant strength in the first layer — a large share of the world's chip-design engineering talent works on Indian soil for multinational firms — but historically lacked the home-grown fabrication base and the structured academic pipeline to convert that talent into Indian-owned products. Chips to Startups (C2S) is the programme aimed squarely at that pipeline: it seeds VLSI (Very Large Scale Integration) and chip-design capability inside colleges so that the next generation of engineers learns the full silicon journey, not just simulation.

C2S works by putting professional EDA software — the same category of tools commercial chip companies use — into the hands of students, and then letting their designs actually be manufactured. That second half is what makes the programme unusual: the Semiconductor Laboratory (SCL) at Mohali, Punjab, a government fab under MeitY, fabricates and tests student designs so learners experience real tape-out rather than purely virtual exercises. The "Semicon 2.0" framing reflects a stated second phase of the mission, extending the institutional footprint and signalling continuity of the policy beyond its first set of approvals.

A word on the tools and the lab, because both are examinable in their own right. EDA (Electronic Design Automation) is the software layer used to design, simulate and verify integrated circuits before they are ever physically made; without it a modern chip carrying billions of transistors cannot be laid out by hand. The named partners cover the commercial spine of this industry: Synopsys, Cadence and Siemens EDA are the leading design-tool vendors, while Renesas (a chipmaker), Ansys (simulation) and AMD (processors) round out the design-to-validation chain. Making such tools available "open-access" inside colleges removes a cost barrier that would otherwise keep cutting-edge VLSI design out of most Indian classrooms. The Semiconductor Laboratory, Mohali is one of the few government-run fabrication facilities in the country; originally set up to serve strategic and space-electronics needs, it now doubles as the manufacturing partner that turns student designs into real silicon, which is what lets C2S claim genuine end-to-end exposure.

It is worth situating this against India's existing position. India is widely regarded as home to a very large share of the world's semiconductor design talent, with the engineering centres of most global chip companies operating in cities such as Bengaluru, Hyderabad and NCR. The strategic argument the Ministry is making is that this design strength should now feed an Indian-owned manufacturing and product ecosystem rather than only serving foreign firms — and that doing so requires multiplying the talent base far beyond the current intake. C2S, by widening from 315 to 500 institutions, is the supply-side instrument for that multiplication, while the fab-incentive and DLI schemes work the demand and capital side.

For Prelims

Full forms: ISM = India Semiconductor Mission · C2S = Chips to Startups · EDA = Electronic Design Automation · SCL = Semiconductor Laboratory · ATMP = Assembly, Testing, Marking and Packaging.
Nodal ministry/body: Ministry of Electronics & Information Technology (MeitY); ISM functions as a division under the Digital India Corporation.
Umbrella programme: Semicon India Programme; ISM is the implementing mission within it.
C2S target: train 85,000 engineers in semiconductor design over a ten-year horizon (design, verification and related skills).
Current reach: EDA tools in 315 institutions → to expand to 500 under Semicon 2.0.
Industry partners supplying tools: Synopsys, Cadence, Siemens (EDA), Renesas, Ansys and AMD.
Fabrication/testing hub: SCL, Mohali (Punjab) — a MeitY-owned semiconductor fab that lets student designs be physically made.
Scale claim: described as the world's largest open-access EDA programme, with over 1.85 crore hours of tool usage logged.
Market context: global semiconductor industry moving from ~USD 800–900 billion toward ~USD 2 trillion, with demand for ~2 million skilled professionals.
What it is NOT: C2S is not a fabrication-plant subsidy and not an incentive for commercial fabs — that role belongs to the separate fiscal-support schemes for fabs, display fabs, compound semiconductors and ATMP/OSAT units. C2S is a design-skilling and academic-ecosystem programme. It is also not the DLI (Design Linked Incentive) scheme, which gives financial incentives to domestic chip-design companies and startups; C2S sits upstream of DLI, building the talent that DLI-backed firms hire. Semicon 2.0 is a phase of ISM, not a new separate mission.
The wider ISM family (the full set): (1) Scheme for Setting up of Semiconductor Fabs · (2) Scheme for Setting up of Display Fabs · (3) Scheme for Compound Semiconductors / Silicon Photonics / Sensors / Discrete Semiconductors and ATMP/OSAT · (4) Design Linked Incentive (DLI) Scheme · (5) the talent/ecosystem layer that C2S serves. Knowing this five-part set lets you survive "how many of these come under ISM" questions.

For UPSC: C2S (under ISM, MeitY) targets 85,000 chip-design engineers in 10 years; EDA tools in 315 → 500 institutions under Semicon 2.0; student designs fabricated and tested at SCL Mohali. Distinguish C2S (design skilling) from the fab-subsidy schemes and from DLI (incentives to design firms).

Why it matters

The strategic problem C2S addresses is structural. India consumes a very large and growing volume of semiconductors — for phones, vehicles, defence systems, telecom gear and consumer electronics — yet for decades imported almost all of them, leaving a wide trade gap and a supply-chain vulnerability exposed sharply during the global chip shortage. Manufacturing capacity takes years and tens of thousands of crores to build; but even a finished fab is useless without a deep bench of engineers who can design chips and run advanced process lines. By embedding EDA tools and real fabrication access inside hundreds of colleges, C2S tries to manufacture that bench at the front end, so that as fabs come online India has the people to staff and feed them.

There is also an economic-geography argument. A semiconductor ecosystem clusters: design houses, fabs, packaging units, materials and equipment suppliers, and a steady talent supply tend to co-locate. Widening academic participation "from Assam to Gujarat and Kashmir to Kanyakumari" is an attempt to spread that talent base beyond a few metros, giving the eventual cluster a national catchment. And by letting students take a design all the way to a working die at SCL Mohali, the programme aims to convert India's reputation as a back-office for global chip design into the capacity to own products — the difference between supplying labour and capturing value.

For Mains

Anchor

A question on India's semiconductor strategy or on building indigenous high-technology capability can be answered around ISM and its C2S talent pillar — the design-skilling layer that complements the fabrication-incentive schemes.

Data

Hard figures to substantiate scale: 85,000 ten-year training target, EDA tools in 315 institutions expanding to 500, over 1.85 crore EDA tool-hours, and a global market moving toward ~USD 2 trillion needing ~2 million professionals.

Example

C2S is a concrete, citable example of public-private skilling — government access to commercial EDA tools (Synopsys, Cadence, Siemens, Renesas, Ansys, AMD) plus government fabrication at SCL Mohali — that turns classrooms into chip-design and tape-out training grounds.

Problem

It illustrates the talent-pipeline gap behind India's import dependence in electronics: hardware self-reliance needs not just fabs but tens of thousands of trained design engineers, a constraint that physical incentives alone cannot fix.

Way forward

Deepening academic-industry linkages, expanding institutional reach (the 315→500 step), and pairing skilling with fabrication access point to a way of building an end-to-end domestic semiconductor ecosystem rather than isolated plants.

Deploys into: indigenisation and new technology (GS3.12), IT/electronics and emerging technologies (GS3.13), inclusive growth and skilling, and India's drive for self-reliance in strategic supply chains.

Ministry of Electronics & IT · 2026-03-07 · PRID 2236290 · PIB source ↗